Jeffrey Sung

3-Stage Pipelined RISC-V CPU

Digital design, Electrical engineering 3-Stage Pipelined RISC-V CPU

By Billy Bao & Jeffrey Sung 12 December 2022

Includes UART for tethering and a branch predictor.

2-Stage Pipelined RISC-V CPU

Machine structures 2-Stage Pipelined RISC-V CPU

By Jeffrey Sung 12 April 2021

Designed two-stage pipelined CPU that runs the full RISC-V instruction set.