Digital design,
Electrical engineering
3-Stage Pipelined RISC-V CPU
Includes UART for tethering and a branch predictor.
read moreIncludes UART for tethering and a branch predictor.
read moreDesigned two-stage pipelined CPU that runs the full RISC-V instruction set.
read moreA simple artificial neural network written only using RISC-V.
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